Semiconductor device technologies continue to evolve, providing higher chip density and operating frequencies. Fin-type field-effect transistors (FINFETs) are one type of transistor technology that is being used to help provide desired device scaling while maintaining appropriate power consumption budgets.
U.S. Pat. Pub. No. 2010/0203732 discloses a FINFET device and related method, in which each FINFET may have a width of sub-lithographic dimension. The method includes forming a mask having a plurality of openings atop a semiconductor-containing layer which is located on a substrate. An angled ion implantation is then performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is thereafter removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern. The pattern is then transferred into the substrate to provide a fin structure having a width of sub-lithographic dimension.
Another type of FINFET device is the multi-fin FINFET. This device typically includes a plurality of spaced apart semiconductor fins with a tri-gate that overlies the fins. The effective gate width of a FINFET is 2 nh, where n is the number of fins and h is the fin height. Thus, wider transistors with higher on-currents may be obtained by using multiple fins. Yet, higher numbers of fins may result in more complicated devices structures that can pose challenges to fabricate.